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19-2189; Rev 1; 2/02
Low-Cost Integrated Offset Logic for Notebook CPU Power Supplies
General Description
The MAX1888 is a three-input decoder with three opendrain outputs. It is used with the MAX1718 or a similar DC-to-DC controller to offset the CPU core voltage in notebook computers. Designed to interface with lowvoltage logic, the MAX1888 can program the controller for three independent offsets. The circuit is extremely low cost and is available in an 8-pin MAX package.
Features
o Simple, Low-Cost Offset Voltage Control for CPU Core Power Supplies o IMVP II Logic Interface o 3V to 5.5V Supply Voltage o Low 30A (max) Supply Current o 8-Pin MAX Package
MAX1888
Applications
CPU Core Supplies for Intel IMVP II Notebook Computers
PART MAX1888EUA
Ordering Information
TEMP RANGE -40C to +85C PIN-PACKAGE 8 MAX
Minimal Operating Circuit
TOP VIEW
POS VCC MAX1888 NEG LOWVOLTAGE LOGIC INPUTS DPSLP PERF SUS GND BSM PSM BOM OPEN-DRAIN DECODER OUTPUTS OFFSET ADJUST DPSLP PERF SUS GND 1 2 3 4
Pin Configuration
INPUT SUPPLY
8
VCC BSM PSM BOM
MAX1888
7 6 5
MAX
________________________________________________________________ Maxim Integrated Products
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Low-Cost Integrated Offset Logic for Notebook CPU Power Supplies MAX1888
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V to +6V PERF, SUS, DPSLP, BOM, PSM, BSM to GND ........-0.3V to +6V Continuous Power Dissipation 8-Pin MAX (derate 4.5mW/C above +70C) ...........362.0mW Extended Operating Temperature.......................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature.........................................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VCC = +5V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER POWER SUPPLY Supply Voltage Range (VCC) BIAS Quiescent Supply Current (VCC) LOGIC AND I/Os Logic Input High Voltage (PERF, SUS, DPSLP), Hysteresis = 40mV (typ) Logic Input Low Voltage (PERF, SUS, DPSLP), Hysteresis = 40mV (typ) Logic Input Current Output On-Resistance (BOM, BSM, PSM) Output Leakage Current (BOM, BSM, PSM) DYNAMICS Falling edge, 1.5V to 0V step in 2ns Propagation Delay Rising edge, 0 to 1.5V step in 2ns 700 70 ns ILOAD = 5mA ILOAD = 5mA, 3V < VCC < 5.5V V(pin) = 5V < 0.01 3V < VCC < 5.5V 1.2 V All inputs = 0 All inputs = 1.5V < 0.01 10 1 30 A 3.0 5.5 V CONDITIONS MIN TYP MAX UNITS
0.4 V 3V < VCC < 5.5V -1 20 0.3 1 50 100 1 A A
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Low-Cost Integrated Offset Logic for Notebook CPU Power Supplies
Typical Operating Characteristics
(Circuit of Figure 1, logic high = 1.5V, VOUT = 1.3V, TA = +25C, unless otherwise noted.)
MAX1888
SUPPLY CURRENT vs. SUPPLY VOLTAGE
100
MAX1888toc01
SUPPLY CURRENT VS. TEMPERATURE
MAX1888 toc02
OUTPUT RON VS. SUPPLY VOLTAGE
TA = +85C TA = +25C 30 TA = -40C RON ()
MAX1888 toc03
16 A B SUPPLY CURRENT (A) 12 VCC = 5V
40 35
10 SUPPLY CURRENT (A)
1
8 VCC = 4.5V 4 VCC = 3.3V 0
25 20 15 10
0.1 C D 0.01
0.001 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) A = ALL INPUTS = 1.5V B = ALL INPUTS = 3.3V C = ALL INPUTS = 5V D = ALL INPUTS = 0.4V
-40
-15
10
35
60
85
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (C)
VCC (V)
OUTPUT RON VS. TEMPERATURE
MAX1888 toc04
SWITCHING CHARACTERISTICS (OUTPUT TRANSITIONS INTO A 10k LOAD)
MAX1888 toc05
SWITCHING CHARACTERISTICS (OUTPUT TRANSITIONS INTO A 10k LOAD)
MAX1888 toc06
40 35 VCC = 3.3V 30 RON () 25 20 15 10 -40 -15 10 35 60 VCC = 5V
A A
B
VCC = 3.3V B
VCC = 5V VCC = 3.3V 400ns/div A = VIN, 1V/div B = VOUT, 1V/div
VCC = 5V 85 A = VIN, 1V/div B = VOUT, 1V/div 20ns/div
TEMPERATURE (C)
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME DPSLP PERF SUS GND BOM PSM BSM VCC FUNCTION Deep-Sleep Mode Control Digital Input Performance-Mode Offset Control Digital Input Suspend-Mode (Deeper Sleep) Control Digital Input Ground Open-Drain Output for Battery Operating Mode (BOM) Open-Drain Output for Performance Sleep Mode (PSM) Open-Drain Output for Battery Sleep Mode (BSM) Supply Voltage
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Low-Cost Integrated Offset Logic for Notebook CPU Power Supplies MAX1888
TTable 1. Truth Table
INPUTS MODE Deeper Sleep Battery Sleep Performance Sleep Battery Operating Performance DPSLP X L L H H PERF X L H L H SUS H L L L L BSM Hi-Z L Hi-Z Hi-Z Hi-Z OUTPUTS PSM Hi-Z Hi-Z L Hi-Z Hi-Z BOM Hi-Z Hi-Z Hi-Z L Hi-Z
Detailed Description
The MAX1888 is a three-input decoder with three opendrain outputs. It is used with the MAX1718 DC-to-DC controller to offset the CPU core voltage in notebook computers. The MAX1718 has two dedicated inputs (POS and NEG) that simplify the task of offsetting its output voltage. Specifically, the output voltage shifts by an amount equal to the difference between POS and NEG multiplied by a scale factor that depends on the DAC code (refer to the MAX1718 data sheet). The voltage between the POS and NEG inputs can be set with a programmable voltage-divider using the MAX1888 to connect the bottom resistor of the divider to ground (see Figure 1.)
Logic Characteristics
The Intel mobile processor specifications require independent offset to the CPU core voltage for battery sleep mode (BSM), performance sleep mode (PSM) and battery-operating mode (BOM). No offsets are required for the deeper-sleep mode (DPSLP) and performance mode (PERF). Table 1 explicitly describes the logical operation of the decoder. The decoder's inputs may come from system-level logic or directly from the CPU. To interface with lowvoltage logic, the MAX1888's input logic thresholds are designed with an input-logic high voltage of 1.2V (min) and an input-logic low voltage of 0.3V (max). The logic inputs also include 40mV (typ) hysteresis to improve noise immunity. The output on-resistance is guaranteed to be less than 100 over the entire supply voltage and temperature range. When loaded with a total pullup resistance greater than 10k, the open-drain output resistance causes less than 1% error in impedance. If the offset voltage is set to 5% of the regulated output voltage, then the effect of the impedance error on the output voltage is approximately 0.05%, which is negligible in most applications. The MAX1888 has rising- and falling-edge propagation delays of 70ns (typ) and 700ns (typ), respectively. Since transition times for CPU core voltage are typically much longer than these intervals, such delays are negligible. Note the time constant of the rising edge in the output voltage is set by the capacitance of the opendrain output transistor and the load impedance (see the Typical Operating Characteristics).
VOUT NEG TO MAX1718 POS VCC MAX1888 LOWVOLTAGE LOGIC INPUTS DPSLP PERF SUS GND BSM PSM BOM OPEN-DRAIN DECODER OUTPUTS
5V INPUT
Figure 1. Simplified Application Circuit; Also Used for Obtaining Characterization Data; Offset Voltage is a Percentage of the Output Voltage.
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Low-Cost Integrated Offset Logic for Notebook CPU Power Supplies MAX1888
R1 20 C8 0.1F 2 10 25 24 R2 100k R3 100k 23 9 VCC SKP/SDN TON D0 D1 D2 MAX1718 D3 D4 GND 19 MUX CONTROL REF SUSPEND INPUT DECODER R4 62k C6 47pF 6 C5 0.22F 11 R18 24.9k R19 27.4k REF VGATE 12 ILIM OVP 14 20 CC 7 8 18 ZMODE SUS S0 S1 NEG 5 FB DL LX 27 2x 16 15 MAX1888 4 7 6 5 BSM PSM BOM DPSLP PERF SUS GND R10 1k POS 13 5V R5 100k POWER-GOOD OUTPUT R11 26.7k R12 15.8k R13 82.5k 1 2 3 4 LOGIC INPUTS FDS7764A Q2 17 VDD V+ BST 1 26 D1 CMPSH-3 2x 28 IRF7811A Q1 C3 0.1F L1 0.68H SUMIDA CEP125#4712-TO11 D2 CENTRAL SEMICONDUCTOR CMSH5-40 R8 0.004 OUTPUT 0.6V TO 1.75V C4 6 x 270F, 2V PANASONIC SP EEFUE0E271R VCC 8 C7 0.1F C2, 25V, X5R 5 x 10F 5V INPUT C1 0.22F
BATT 7V TO 24V
SHUTDOWN VCC
DH
22 21
5V INPUT
3
TIME
Figure 2. Typical Application Circuit
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Low-Cost Integrated Offset Logic for Notebook CPU Power Supplies MAX1888
Supply Current
The MAX1888 needs no shutdown control. The circuit consumes virtually no current (I(VCC) < 1A) when all the logic inputs are 0V, and less than 30A when all the logic inputs are 1.5V. In general, the supply current increases with supply voltage and decreases with the logic input voltage. For a given supply voltage, the supply current decreases with temperature (see the Typical Operating Characteristics).
VREF NEG TO MAX1718 POS VCC MAX1888 LOWVOLTAGE LOGIC INPUTS DPSLP PERF SUS GND BSM PSM BOM OPEN-DRAIN DECODER OUTPUTS
5V INPUT
Applications Information
Figure 2 shows a typical CPU core supply application using the MAX1888 and the MAX1718. The voltage dividers are set to obtain negative offsets of 1%, 3%, and 5% of the output voltage for battery-operating mode (BOM), battery sleep mode (BSM), and performance sleep mode (PSM), respectively. The offset voltage is given by the following equation: VOFFSET = K (VPOS - VNEG ) where K is the DAC code-dependent scale factor (refer to Table 3 in the MAX1718 data sheet). The offset voltage in each mode is: VOFFSET, BOM = - K VOFFSET, BSM = - K VOFFSET, PSM = - K R10 R10 + R13 R10 R10 + R11 R10 R10 + R12 VOUT
Figure 3. Using the MAX1888 to Set the Offset Voltage Independent of VOUT
The MAX1888 can be inserted in the feedback path of any regulator to offset the output voltage. An external reference greater than the feedback set point is needed to affect negative offsets. The basic arrangement is shown in Figure 4.
VREF VOUT
VOUT
5V INPUT
VOUT
VFB VCC MAX1888 LOWVOLTAGE LOGIC INPUTS DPSLP PERF SUS GND BSM PSM BOM OPEN-DRAIN DECODER OUTPUTS
Note that divider ratio in each mode must be adjusted for a given DAC code. The circuit in Figure 2 assumes VOUT = 1V with K = 0.84 and R10 = 1k. The resulting values for R11, R12, R13 in the divider are 26.7k, 15.8k, and 82.5k, respectively. Please note that these offsets are provided as an example only. Contact Intel for specific offset requirements. The circuits in Figures 1 and 2 set the offset voltage as a percentage of the output voltage. Alternatively, the offset can be set as independent of the output voltage by biasing the POS and NEG inputs from a fixed reference voltage (see Figure 3).
Figure 4. Inserting the MAX1888 into the Feedback Path of Any Regulator to Shift Output Voltage
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Low-Cost Integrated Offset Logic for Notebook CPU Power Supplies
Layout Guidelines
Most applications do not drive the MAX1888 with high frequency signals with ultra-fast transition times. Therefore, the layout requirements are minimal. Keep the resistive voltage-divider traces away from noisy nodes and terminate the dividers through the MAX1888 to quiet analog ground. Place a 0.1F decoupling capacitor close to the device. TRANSISTOR COUNT: 170 PROCESS: CMOS
Chip Information
MAX1888
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
8
4X S
8
INCHES DIM A A1 A2 b c D e E H MIN 0.002 0.030 MAX 0.043 0.006 0.037
MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95
y 0.500.1 0.60.1
E
H
1
0.60.1
1
D
L
S
BOTTOM VIEW
0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6 0 0.0207 BSC
0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 4.78 5.03 0.41 0.66 0 6 0.5250 BSC
TOP VIEW
A2
A1
A
e
c b L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0036
J
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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